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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12517-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89628R/629R/P629
MB89628R/629R/P629
s DESCRIPTION
The MB89628R/629R/P629 have been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers contain a variety of peripheral functions such as timers, serial interfaces, an A/D converter, and an external interrupt. The MB89628R/629R/P629 are applicable to a wide range of applications from welfare to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
* Large-size RAM MB89P629: 4 Kbytes MB89628R: 3 Kbytes MB89629R: 3 Kbytes * High-speed processing at low voltage Minimum execution time: 0.4 s/3.5 V, 0.8 s/2.7 V * F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Instruction set optimized for controllers Test and branch instructions Bit manipulation instructions, etc.
(Continued)
s PACKAGE
64-pin Plastic SH-DIP 64-pin Plastic QFP
(DIP-64P-M01)
(FPT-64P-M06)
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MB89628R/629R/P629
(Continued) * Four types of timers 8-bit PWM timer (also usable as a reload timer) 8-bit pulse width count timer (Continuous measurement capable, applicable to remote control, etc.) 16-bit timer/counter 20-bit time-base timer * Two serial interfaces Swichable the transfer direction allows communication with various equipment. * 8-bit A/D converter Sense mode function enabling comparison at 5 s Activation by an external input capable * External interrupt: 4 channels Four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). * Low-power consumption modes Stop mode (Oscillation stops to reduce the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
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MB89628R/629R/P629
s PRODUCT LINEUP
Part number Parameter
MB89628R
MB89629R
MB89P629
MB89PV620*1
One-time PROM Piggyback/evaluation product for evaluation product for evaluation and development and development ROM size 32 K x 8 bits (internal PROM, 24 K x 8 bits 32 K x 8 bits 32 K x 8 bits programming with (internal mask ROM) (internal mask ROM) (external ROM) general-purpose EPROM programmer) RAM size 3072 x 8 bits 4096 x 8 bits 1 K x 8 bits CPU functions Number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum execution time: 0.4 s/10 MHz Interrupt processing time: 3.6 s/10 MHz Ports Input ports: 5 (4 ports also serve as peripherals.) Output ports (N-ch open-drain): 8 (All also serve as peripherals.) I/O ports (N-ch open-drain): 8 (4 ports also serve as peripherals.) Output ports (CMOS): 8 I/O ports (CMOS): 24 Total: 53 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 s to 3.3 ms) 8-bit PWM timer 8-bit resolution PWM operation (conversion cycle: 102 s to 839 ms) 8-bit pulse width count 8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 s) timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 s) 8-bit pulse width measurement operation (Continuous measurement "H" pulse width/"L" pulse width/from to /from to capable) 16-bit timer/counter 16-bit timer operation (operating clock cycle: 0.4 s) 16-bit event counter operation (Rising/falling/both edges selectability) 8-bit serial I/O 1, 8-bits 8-bit serial I/O 2 LSB first/MSB first transfer selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 s, 3.2 s, 12.8 s) 8-bit A/D converter 8-bit resolution x 8 channels A/D conversion mode (conversion time: 18 s) Sense mode (conversion time: 5 s) Continuous activation by an external activation or an internal timer capable Reference voltage input External interrupt 4 independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge selectability Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) Standby modes Sleep mode, stop mode Process CMOS 2.2 V to 6.0 V 2.7 V to 6.0 V Operating voltage*2 EPROM for use MBM27C256A-20 Classification Mass production products (mask ROM products) *1: The piggyback/evaluation product is applicable to the MB89620 series. *2: Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") In the case of the MB89PV620, the voltage varies with the restrictions of the EPROM for use. 3
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MB89628R/629R/P629
s PACKAGE AND CORRESPONDING PRODUCTS
Package DIP-64P-M01 FPT-64P-M06 MDP-64C-P02 MQP-64C-P01 : Available x x MB89628R MB89629R MB89P629 MB89PV620 x x
x : Not available
Note: For more information about each package, see section "s Package Dimensions."
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: * On the MB89P629, the program area starts from address 8007H but on the MB89PV620, MB89628R, and MB89629R starts from 8000H. (On the MB89P629, addresses 8000H to 8006H comprise the option setting area, option settings can be read by reading these addresses. On the MB89PV620, MB89628R, and MB89629R, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P629.)
2. Current Consumption
* In the case of the MB89PV620, add the current consumed by the EPROM which is connected to the top socket. * When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see section "s Electrical Characteristics".)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section "s Mask Options." Take particular care on the following points: * A pull-up resistor cannot be set for P40 to P47 on the MB89P629. * A pull-up resistor is not selected for P50 to P57 when the A/D converter is used. * Options are fixed on the MB89PV620.
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MB89628R/629R/P629
s PIN ASSIGNMENT
(Top view) P36/WTO P37/PTO P40 P41 P42 P43 P44/BZ P45/SCK2 P46/SO2 P47/SI2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 P64 RST MOD0 MOD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (DIP-64P-M01) (Top view) P44/BZ P43 P42 P41 P40 P37/PTO P36/WTO VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 P30/ADST/CLKO VSS P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27
P45/SCK2 P46/SO2 P47/SI2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 P64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P30/ADST/CLKO VSS P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20
RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 (FPT-64P-M06)
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MB89628R/629R/P629
s PIN DESCRIPTION
Pin no. SH-DIP*1 30 31 28 29 27 QFP*2 23 24 21 22 20 Pin name X0 X1 MOD0 MOD1 RST C B Operating mode selection pins Connect directly to VCC or VSS. Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. "L" is output from this pin by an internal reset source. The internal circuit is initialized by the input of "L". General-purpose I/O ports General-purpose output-only ports Circuit type A Cystal oscillator pins Function
56 to 49 48 to 41 40, 39 38, 37 36 to 33 58
49 to 42 41 to 34 33, 32 31, 30 29 to 26 51
P00 to P07 P10 to P17 P20, P21 P22, P23 P24 to P27 P30/ADST/ CLKO
D D F D F E
General-purpose I/O port Also serves as an A/D converter external activation and an oscillation monitor clock output. This port is a hysteresis input type. General-purpose I/O port Also serves as the clock I/O for the 8-bit serial I/O 1. This port is a hysteresis input type. General-purpose I/O port Also serves as the data output for the 8-bit serial I/O 1. This port is a hysteresis input type. General-purpose I/O port Also serves as the data input for the 8-bit serial I/O 1. This port is a hysteresis input type. General-purpose I/O port Also serves as the external clock input for the 16-bit timer/ counter. This port is a hysteresis input type. General-purpose I/O port Also serves as the measured pulse input for the 8-bit pulse width count timer. This port is a hysteresis input type. General-purpose I/O port Also serves as the toggle output for the 8-bit pulse width count timer. This port is a hysteresis input type.
59
52
P31/SCK1
E
60
53
P32/SO1
E
61
54
P33/SI1
E
62
55
P34/EC
E
63
56
P35/PWC
E
1
58
P36/WTO
E
*1: DIP-64P-M01 *2: FPT-64P-M06
(Continued)
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MB89628R/629R/P629
(Continued) Pin no.
SH-DIP*1 2 QFP*2 59
Pin name P37/PTO
Circuit type E
Function General-purpose I/O port Also serves as the toggle output for the 8-bit PWM timer. This port is a hysteresis input type. N-ch open-drain I/O ports These ports are a hysteresis input type. N-ch open-drain I/O port Also serves as a buzzer output. This port is a hysteresis input type. N-ch open-drain I/O port Also serves as the clock I/O for the 8-bit serial I/O 2. This port is a hysteresis input type. N-ch open-drain I/O port Also serves as the data output for the 8-bit serial I/O 2. This port is a hysteresis input type. N-ch open-drain I/O port Also serves as the data input for the 8-bit serial I/O 2. This port is a hysteresis input type. N-ch open-drain output-only port Also serves as the analog input for the A/D converter. General-purpose input-only ports Also serve as an external interrupt input. These ports are a hysteresis input type. General-purpose input-only port This port is a hysteresis input type. Power supply pin Power supply (GND) pins A/D converter power supply pin A/D converter reference voltage input pin A/D converter power supply (GND) pin. Use this pin at the same voltage as VSS.
3 to 6 7
60 to 63 64
P40 to P43 P44/BZ
G G
8
1
P45/SCK2
G
9
2
P46/SO2
G
10
3
P47/SI2
G
11 to 18 22 to 25
4 to 11 15 to 18
P50/AN0 to P57/AN7 P60/INT0 to P63/INT2 P64 VCC VSS AVCC AVR AVSS
H I
26 64 32, 57 19 20 21
19 57 25, 50 12 13 14
I -- -- -- -- --
*1: DIP-64P-M01 *2: FPT-64P-M06
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MB89628R/629R/P629
s I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks * At an oscillation feedback resistor of approximately 1 M/5.0 V
X0
Standby control signal
B C
R P-ch
* At an output pull-up resistor (P-ch) of approximately 50 M/5.0 V * CMOS hysteresis input
N-ch
D
R P-ch P-ch
* CMOS output * CMOS input
N-ch
* Pull-up resistor optional (except P22 and P23) E
R P-ch P-ch
* CMOS output * Hysteresis input
N-ch
* Pull-up resistor optional F
P-ch
* CMOS output
N-ch
(Continued)
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MB89628R/629R/P629
(Continued)
Type G
R P-ch P-ch
Circuit
Remarks * N-ch open-drain output * Hysteresis input
N-ch
* Pull-up resistor optional (MB89628R and MB89629R only) H
R P-ch
* N-ch open-drain output * Analog input
N-ch Analog input
I
R
* Hysteresis input
* Pull-up resistor optional
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MB89628R/629R/P629
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
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MB89628R/629R/P629
s PROGRAMMING TO THE EPROM ON THE MB89P629
The MB89P629 is an OTPROM version of the MB89628R and MB89629R.
1. Features
* 16-Kbyte PROM on chip * Options can be set using the EPROM programmer. * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode, option area is diagrammed below.
Address 0000H 0080H 0100H Register 0200H 1080H 8000H Not available 0000H Option area 8007H 0007H Option area I/O Single chip EPROM mode (Corresponding addresses on the EPROM programmer)
RAM
Program area (EPROM) 32 KB
PROM 32 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P629 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. * Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH (note that addresses 8000H to FFFFH while operating as a single chip assign to 0000H to 7FFFH in EPROM mode. For information about each corresponding option, see "7. Setting OTPROM Options.") (3) Program to 0000H to 7FFFH with the EPROM programmer. 11
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MB89628R/629R/P629
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package DIP-64P-M01 FPT-64P-M06 Compatible socket adapter ROM-64SD-28DP-8L ROM-64QF-28DP-8L
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
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MB89628R/629R/P629
7. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: * OTPROM option bit map Bit 7 Bit 6 Bit 5 Bit 4 Oscillation stabilization time 1: Crystal 0: Ceramic P04 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P54 Pull-up 1: No 0: Yes P64 Pull-up 1: No 0: Yes Bit 3 Reset pin output 1: Yes 2: No P03 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P53 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes Bit 2 Power-on reset 1: Yes 0: No P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P52 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes Bit 1 Vacancy Bit 0 Vacancy
Vacancy Vacancy Vacancy 8000H (0000H) Readable and Readable and Readable and writable writable writable P07 8001H Pull-up (0001H) 1: No 0: Yes P17 8002H Pull-up (0002H) 1: No 0: Yes P37 8003H Pull-up (0003H) 1: No 0: Yes P57 8004H Pull-up (0004H) 1: No 0: Yes P06 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P56 Pull-up 1: No 0: Yes P05 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P55 Pull-up 1: No 0: Yes
Readable and Readable and writable writable P01 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P51 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P50 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes
Vacancy Vacancy Vacancy 8005H (0005H) Readable and Readable and Readable and writable writable writable
Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Reserved bit 8006H (0006H) Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and writable writable writable writable writable writable writable writable Notes: * Set each bit to 1 to erase. * Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. * Always write 0 to the reserved bit.
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MB89628R/629R/P629
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV, MBM27C256A-20CZ
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in 32-Kbyte PROM on the EPROM programmer is diagrammed below.
Address 0000H 0080H I/O Single chip Corresponding addresses on the EPROM programmer
RAM 0480H 8000H Not available Not available 8007H 0007H 0000H Not available
PROM 32 KB
EPROM 32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer.
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MB89628R/629R/P629
s BLOCK DIAGRAM
X0 X1
Oscillator
20-bit time-base timer
Internal bus
Clock controller
8-bit PWM timer
P37/PTO
RST
Reset circuit (WDT)
8-bit pulse width count timer Port 3
P36/WTO P35/PWC
8 P00 to P07 8 P10 to P17 MOD0 MOD1
Port 0 and port 1
CMOS I/O port 16-bit timer/counter
P34/EC
8-bit serial I/O 1 External bus interface CMOS I/O port
P33/SI1 P32/SO1 P31/SCK1 P30/ADST/CLKO
Port 2
8 P20 to P27
8-bit serial I/O 2 Port 4
P47/SI2 P46/SO2 P45/SCK2 P44/BZ 4 P40 to P43
CMOS output port
Buzzer output
N-ch open-drain I/O port N-ch open-drain output port Port 5
RAM
8 F2MC-8L CPU 8-bit A/D converter
8
P50/AN0 to P57/AN7 AVR AVCC AVSS
ROM Port 6 External interrupt 4 4
P60/INT0 to P63/INT3 P64
Other pins VCC, VSS x 2
Input port
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MB89628R/629R/P629
s CPU CORE
1. Memory Space
The microcontrollers of the MB89628R/629R/P629 offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89628R/629R/P629 is structured as illustrated below. Memory Space
0000H MB89PV620 I/O 0080H RAM * 1 KB 0100H Register 0200H 0480H External area 8000H 0C80H 0C80H Not available Not available A000H External ROM 32 KB ROM 24 KB ROM 32 KB ROM 32 KB 8000H 1080H 8000H 8007H Not available Option area*2 0200H
1
0000H
MB89628R I/O
0000H
MB89629R I/O
0000H
MB89P629 I/O
0080H RAM 3 KB 0100H Register
0080H RAM 3 KB 0100H Register 0200H
0080H RAM 4 KB 0100H Register 0200H
FFFFH
FFFFH
FFFFH
FFFFH
*1: The internal RAM of the MB89PV620 is 1 Kbyte. The RAM of a development tool can be substituted for that RAM when the tool is connected. If the MB89PV620 is used as a piggyback product, however, it runs out of RAM. Note, in addition, that some tools such as the MB2140 series cannot be used due to mapping restrictions. *2: Since addresses 8000H to 8006H for the MB89P629 comprise an option area, do not use this area for the MB89PV620, MB89628R, and MB89629R.
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MB89628R/629R/P629
3. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided:
Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS):
A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code
16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15 PS
14
13 RP
12
11
10
9
8
7 H
6 I
5
4
3 N
2 Z
1 V
0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
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MB89628R/629R/P629
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit.
IL1 0 0 1 1
IL0 0 1 0 1
Interrupt level 1 2 3
High-low High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction.
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MB89628R/629R/P629
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89628R and MB89629R. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
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MB89628R/629R/P629
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) (R/W) (R/W) SMR1 SDR1 SMR2 SDR2 (R/W) (R/W) (R/W) TMCR TCHR TCLR (R/W) (W) (R/W) (R/W) (R/W) (R) (R/W) (W) (R/W) (R/W) (R/W) PDR3 DDR3 PDR4 BZCR PDR5 PDR6 CNTR COMR PCR1 PCR2 RLBR (R/W) (R/W) (R/W) STBC WDTC TBTC Read/write (R/W) (W) (R/W) (W) (R/W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 BCTR Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register External bus pin control register Vacancy Vacancy Standby control register Watchdog timer control register Time-base timer control register Vacancy Port 3 data register Port 3 data direction register Port 4 data register Buzzer register Port 5 data register Port 6 data register PWM control register PWM compare register PWC pulse width control register 1 PWC pulse width control register 2 PWC reload buffer register Vacancy 16-bit timer control register 16-bit timer count register (H) 16-bit timer count register (L) Vacancy Serial I/O 1 mode register Serial I/O 1 data register Serial I/O 2 mode register Serial I/O 2 data register
(Continued)
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MB89628R/629R/P629
(Continued)
Address 20H 21H 22H 23H 24H 25H 26H 27H to 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) (R/W) EIC1 EIC2 CLKE Read/write (R/W) (R/W) (R/W) Register name ADC1 ADC2 ADCD Register description A/D converter control register 1 A/D converter control register 2 A/D converter data register Vacancy External interrupt control register 1 External interrupt control register 2 Clock output control register Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy
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MB89628R/629R/P629
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter Power supply voltage A/D converter reference input voltage Input voltage
Symbol VCC AVCC AVR VI VI2 VO VO2 IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 -55 Max. VSS + 7.0 VSS + 7.0 VCC + 0.3 VSS + 7.0 VCC + 0.3 VSS + 7.0 20 4 100 40 -20 -4 -50 -20 300 +85 +150
Unit V V V V V V mA mA mA mA mA mA mA mA mW C C *1
Remarks
AVR must not exceed AVCC + 0.3 V. Except P40 to P47*2 P40 to P47 Except P40 to P47*2 P40 to P47
Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
Average value (operating current x operating rate)
Average value (operating current x operating rate)
Average value (operating current x operating rate)
Average value (operating current x operating rate)
*1: Use AVCC and VCC set at the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. *2: VI and VO must not exceed VCC + 0.3 V. Precautions: Permanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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MB89628R/629R/P629
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value Min. 2.2* Max. 6.0* 6.0* 6.0 AVCC +85
Unit V V V V C
Remarks Normal operation assurance range* (MB89628R/629R) Normal operation assurance range* (MB89P629/PV620) Retains the RAM state in stop mode
Power supply voltage
VCC AVCC
2.7* 1.5
A/D converter reference input voltage Operating temperature
AVR TA
0.0 -40
* : These values vary with the operating frequency and analog assurance range. See Figure 1 and "5. A/D Converter Electrical Characteristics."
6
Operating voltage (V)
5 Operation assurance range 4
Analog accuracy assured in the AVCC = VCC = 3.5 V to 6.0 V range
3
2
1
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Clock operating frequency (at an instruction cycle of 4/Fc) (MHz)
4.0
2.0
0.8
0.4
Minimum execution time (instruction cycle) (s) Note: The shaded area is assured only for the MB89628R/629R.
Figure 1
Operating Voltage vs. Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC.
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MB89628R/629R/P629
3. DC Characteristics
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin P00 to P07, P10 to P17, P22, P23 RST, MOD0, MOD1, P30 to P37, P60 to P64 P40 to P47 P00 to P07, P10 to P17, P22, P23 RST, MOD0, MOD1, P30 to P37, P40 to P47, P60 to P64 P50 to P57 P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57 RST P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P64, MOD0, MOD1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P64, RST
Condition
Value Min. 0.7 VCC Typ. Max. VCC + 0.3
Unit
Remarks
VIH "H" level input voltage
V
VIHS VIHS2 VIL

0.8 VCC 0.8 VCC VSS - 0.3

VCC + 0.3 VSS + 6.0 0.3 VCC
V V V
"L" level input voltage VILS
--
VSS - 0.3 VSS - 0.3 VSS - 0.3

0.2 VCC
V
Open-drain output pin application voltage "H" level output voltage
VD VD2
--
VSS + 0.3 VSS + 6.0
V V
VOH
IOH = -2.0 mA
4.0
V
"L" level output voltage
VOL
IOL = +4.0 mA
0.4
V
VOL2 Input leakage current (Hi-z output leakage current)
--
--
0.4
V
ILI1
0.0 V < VI < VCC
5
A
Without pull-up resistor
Pull-up resistance
RPULL
VI = 0.0 V
25
50
100
k
(Continued)
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MB89628R/629R/P629
(Continued)
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin
Condition FC = 10 MHz Normal operation mode (External clock)
Value Min. -- -- Typ. 9 10 Max. 15 18
Unit mA
Remarks MB89628R, MB89629R
ICC VCC ICCS Power supply current* ICCH
mA MB89P629
FC = 10 MHz Sleep mode (External clock) Stop mode TA = +25C FC = 10 MHz, when A/D conversion is activated
-- --
3 --
4 1
mA A
IA AVCC IAH
--
1
3
mA
FC = 10 MHz, TA = +25C, when A/D conversion is stopped f = 1 MHz
--
--
1
A
Input capacitance
CIN
Other than AVCC, AVSS, VCC, and VSS
--
10
--
pF
* : In the case of the MB89PV620, the current consumed by the connected EPROM and ICE is not included. The power supply current is measured at the external clock.
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MB89628R/629R/P629
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter RST "L" pulse width
Symbol tZLZH
Condition --
Value Min. 16 tXCYL Max. --
Unit ns
Remarks
Note: tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.
tZLZH
RST
0.2 VCC 0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Condition --
Value Min. -- 1 Max. 50 --
Unit ms ms
Remarks Power-on reset function only Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.0 V
tOFF
VCC
0.2 V 0.2 V 0.2 V
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MB89628R/629R/P629
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time
Symbol FC tXCYL PWH PWL tCR tCF
Pin X0, X1 X0, X1 X0 X0
Condition
Value Min. 1 100 Max. 10 1000 -- 10
Unit MHz ns ns ns
Remarks
--
20 --
External clock External clock
X0 and X1 Timing and Conditions
tXCYL PWH tCR 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tCF PWL
X0
0.2 VCC
Clock Conditions
When a crystal or ceramic resonator is used When an external clock is used
X0
X1
X0
X1 Open
(4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol tinst Value (typical) 4/FC Unit s Remarks tinst = 0.4 s when operating at FC = 10 MHz
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MB89628R/629R/P629
(5) Serial I/O Timing
(VCC = +5.0 V10%, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter Serial clock cycle time SCK1 SO1 time SCK2 SO2 time Valid SI1 SCK1 Valid SI2 SCK2 SCK1 valid SI1 hold time SCK2 valid SI2 hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK1 SO1 time SCK2 SO2 time Valid SI1 SCK1 Valid SI2 SCK2 SCK1 valid SI1 hold time SCK2 valid SI2 hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Pin SCK1, SCK2 SCK1, SO1 SCK2, SO2 SI1, SCK1 SI2, SCK2 SCK1, SI1 SCK2, SI2 SCK1, SCK2 SCK1, SCK2 SCK1, SO1 SCK2, SO2 SI1, SCK1 SI2, SCK2 SCK1, SI1 SCK2, SI2
Condition
Value Min. 2 tinst* -200 Max. -- 200 -- -- -- -- 200 -- --
Unit s ns s s s s ns s s
Remarks
Internal shift clock mode
1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst*
External shift clock mode
0 1/2 tinst* 1/2 tinst*
* : For information on tinst, see "(4) Instruction Cycle."
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MB89628R/629R/P629
Internal Shift Clock Mode
tSCYC
SCK1 SCK2
2.4 V 0.8 V 0.8 V
tSLOV
SO1 SO2
2.4 V 0.8 V
tIVSH
tSHIX 0.8 VCC 0.2 VCC
SI1 SI2
0.8 VCC 0.2 VCC
External Shift Clock Mode
tSLSH tSHSL
SCK1 SCK2
0.8 VCC 0.2 VCC 0.2 VCC
0.8 VCC
tSLOV
SO1 SO2
2.4 V 0.8 V
tIVSH
tSHIX 0.8 VCC 0.2 VCC
SI1 SI2
0.8 VCC 0.2 VCC
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MB89628R/629R/P629
(6) Peripheral Input Timing
(VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Peripheral input "H" pulse width 1 Peripheral input "L" pulse width 1 Peripheral input "H" pulse width 2 Peripheral input "L" pulse width 2 Peripheral input "H" pulse width 2 Peripheral input "L" pulse width 2
Symbol tILIH1 tIHIL1 tILIH2 tIHIL2 tILIH2 tIHIL2
Pin PWC, EC, INT0 to INT3
Condition
Value Min. 2 tinst* Max. -- -- -- -- -- --
Unit s s s s s s
Remarks
--
2 tinst* 32 tinst* 32 tinst* 8 tinst* 8 tinst*
A/D mode ADST Sense mode
* : For information on tinst, see "(4) Instruction Cycle."
tIHIL1
tILIH1
PWC EC INT0 to INT3
0.8 VCC 0.2 VCC 0.2 VCC
0.8 VCC
tIHIL2
tILIH2
ADST
0.2 VCC
0.8 VCC 0.2 VCC
0.8 VCC
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MB89628R/629R/P629
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Sense mode conversion time
Symbol
Pin
Condition --
Value Min. -- -- -- -- Typ. -- -- -- -- Max. 8 1.5 1.0 0.9
Unit bit LSB LSB LSB mV mV LSB s s A V V A
Remarks
--
VOT VFST --
AVR = AVCC
AVSS - 1.0 LSB AVSS + 0.5 LSB AVSS + 2.0 LSB AVR - 3.0 LSB AVR - 1.5 LSB -- -- 44 tinst* 12 tinst* -- -- -- AVR 0.5 -- -- 10 AVR AVCC
-- -- -- -- AVR = 5.0 V, when A/D conversion activated AVR = 5.0 V, when A/D conversion stopped AN0 to AN7
-- -- -- 0.0 0.0
Analog port input current IAIN Analog input voltage Reference voltage
IR Reference voltage supply current IRH AVR
--
100
--
--
1
A
* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics." (1) A/D Glossary * Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 8, analog voltage can be divided into 28 = 256. * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("0000 0000" "0000 0001") with the full-scale transition point ("1111 1111" "1111 1110") from actual conversion characteristics * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error (unit: LSB) The difference between theoretical and actual conversion values
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MB89628R/629R/P629
Digital output 1111 1111 1111 1110 Theoretical conversion value Actual conversion value (1 LSB x N + VOT) AVR 256 VNT - (1 LSB x N + VOT) 1 LSB V( N + 1 ) T - VNT -1 1 LSB VNT - (1 LSB x N + 1 LSB) 1 LSB
1 LSB = Linearity error = Differential linearity error = Total error =
0000 0000 0000
0010 0001 0000 VOT VNT V (N + 1)T VFST Analog input
(2) Precautions * Input impedance of the analog input pins The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin. Analog Input Equivalent Circuit
Sample hold circuit C = 33 pF Analog input pin If the analog input impedance is higher than 10 k, it is recommended to connect an external capacitor of approx. 0.1 F. Comparator R = 6 k
. Close for 8 instruction cycles . after activating A/D conversion.
Analog channel selector
* Error The smaller the | AVR - AVSS |, the greater the error would become relatively.
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MB89628R/629R/P629
s INSTRUCTIONS
Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others
Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Instruction Symbols Meaning
(Continued)
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MB89628R/629R/P629
(Continued)
Symbol EP PC SP PS dr CCR RP Ri x (x) (( x )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning
Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction Number of instructions Number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH immediately before the instruction is executed. * 00 becomes 00. N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F.
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MB89628R/629R/P629
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
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MB89628R/629R/P629
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
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MB89628R/629R/P629
(Continued)
Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 TL - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - - NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
37
38
3 PUSHW A SETC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP A A,ext POPW MOV MOVW CLRI A,PS SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F XCH A A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS XCHW XORW ANDW ORW A, T A A A A, T A A A XOR AND OR MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
L
H
0
1
2
0
NOP
SWAP
RET
RETI
1
MULU
DIVU
A
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
2
ROLC
CMP
ADDC
SUBC
A
A
A
s INSTRUCTION MAP
3
RORC
CMPW
ADDCW
SUBCW
A
A
A
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV
CMP
MB89628R/629R/P629
A,dir
A,dir
ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP
6 CMP @EP,#d8
CMP CLRB BBC MOVW MOVW MOVW XCHW MOV CMP ADDC SUBC MOV XOR AND OR MOV dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 CALLV #7 R5 CALLV #6 BLT rel R4 CALLV #5 BGE rel R3 CALLV #4 BZ rel R2 CALLV #3 BNZ rel R1 CALLV #2 BN rel R0 CALLV #1 BP rel CALLV #0 BC rel BNC rel
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8
8
MOV
CMP
A,R0
A,R0
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
9
MOV
CMP
A,R1
A,R1
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
A
MOV
CMP
A,R2
A,R2
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
B
MOV
CMP
A,R3
A,R3
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
C
MOV
CMP
A,R4
A,R4
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
D
MOV
CMP
A,R5
A,R5
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
E
MOV
CMP
A,R6
A,R6
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
F
MOV
CMP
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A,R7
A,R7
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
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MB89628R/629R/P629
s MASK OPTIONS
Model No. Specifying procedure Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P64 Power-on reset With power-on reset Without power-on reset MB89628R/ MB89629R Specify when ordering masking Selectable per pin. (P50 to P57 must be set to without a pull-up resistor when an A/D converter is used.) Selectable MB89P629 Set with EPROM programmer MB89PV620 Setting not possible
1
Can be set per pin. (P40 to P47 are Fixed to without available only for pull-up resistor without a pull-up resistor.) Setting possible Fixed to with power-on reset Fixed to crystal oscillator of 218/FC Fixed to with reset output
2
3
Oscillation stabilization time selection Crystal oscillator: (218/FC) (26.2 ms/10 MHz) Selectable Ceramic oscillator: (214/FC) (1.64 ms/10 MHz) Reset pin output With reset output Without reset output Selectable
Setting possible
4
Setting possible
s ORDERING INFORMATION
Part number MB89628RP-SH MB89629RP-SH MB89P629P-SH MB89628RPF MB89629RPF MB89P629PF MB89PV620C-SH MB89PV620CF Package 64-pin Plastic SH-DIP (DIP-64P-M01) 64-pin Plastic QFP (FPT-64P-M06) 64-pin Ceramic MDIP (MDP-64C-P02) 64-pin Ceramic MQFP (MQP-64C-P01) Remarks
39
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MB89628R/629R/P629
s PACKAGE DIMENSIONS
64-pin Plastic SH-DIP (FPT-64P-M01)
58.00 -0.55 +.008 2.283 -.022
+0.22
INDEX-1 INDEX-2
17.000.25 (.669.010)
5.65(.222)MAX 3.00(.118)MIN 1.00 -0 +.020 .039 -0 1.7780.18 (.070.007) 1.778(.070) MAX 55.118(2.170)REF
+0.50
0.250.05 (.010.002) 0.450.10 (.018.004) 0.51(.020)MIN 15MAX 19.05(.750) TYP
C
1994 FUJITSU LIMITED D64001S-3C-4
Dimensions in mm (inches)
40
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MB89628R/629R/P629
64-pin Plastic QFP (FPT-64P-M06)
24.700.40(.972.016)
51
3.35(.132)MAX
33
20.000.20(.787.008)
0.05(.002)MIN (STAND OFF)
52
32
14.000.20 (.551.008) INDEX
64 20
18.700.40 (.736.016)
12.00(.472) REF
16.300.40 (.642.016)
"A" LEAD No.
1 19
1.00(.0394) TYP
0.400.10 (.016.004)
0.150.05(.006.002) 0.20(.008)
M
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.00(.709)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX
Details of "B" part
0 10 1.200.20 (.047.008)
C
1994 FUJITSU LIMITED F64013S-3C-2
Dimensions in mm (inches)
41
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MB89628R/629R/P629
64-pin Ceramic MDIP (MDP-64C-P02)
56.900.64 (2.240.025) 0~9
15.24(.600) TYP
18.750.30 (.738.012)
19.050.30 (.750.012)
INDEX AREA
2.540.25 (.100.010) 33.02(1.300)REF
0.250.05 (.010.002)
10.16(.400)MAX
1.270.25 (.050.010)
1.7780.25 (.070.010)
0.46 -0.08 +.005 .018 -.003 55.12(2.170)REF
+0.13
0.900.13 (.035.005)
3.430.38 (.135.015)
C
1994 FUJITSU LIMITED M64002SC-1-4
Dimensions in mm (inches)
42
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MB89628R/629R/P629
64-pin Ceramic MQFP (MQP-64C-P01)
18.70(.736)TYP 16.300.33 (.642.013) 15.580.20 (.613.008) 12.00(.472)TYP 1.20 -0.20 +.016 .047 -.008
+0.40
INDEX AREA
1.000.25 (.039.010)
1.000.25 (.039.010)
1.270.13 (.050.005) 22.300.33 (.878.013) 24.70(.972) TYP 0.30(.012) TYP 18.120.20 12.02(.473) (.713.008) TYP 10.16(.400) 14.22(.560) TYP TYP
18.00(.709) TYP
1.270.13 (.050.005)
0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP
0.400.10 (.016.004)
0.400.10 (.016.004)
1.20 -0.20 +.016 .047 -.008
+0.40
0.50(.020)TYP
10.82(.426) 0.150.05 MAX (.006.002)
C
1994 FUJITSU LIMITED M64004SC-1-3
Dimensions in mm (inches)
43
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MB89628R/629R/P629
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED
Printed in Japan
44

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